One of the parameters which is tested to determine whether an IC chip is defective is I/O pin leakage current. A drawback in testing for leakage current has been the excessive test time that has been required. As illustrated by the prior art circuit of FIG. 1, test methods in common use apply a voltage through a large current sensing resistor to the pin under test, and measure any current which results therefrom by knowing the value of the resistance provided by the resistor, and determining the voltage across the resistor. Tests are conducted for both high voltage and low voltage leakage. Thus, when testing for high voltage leakage, a high voltage is applied to the pin under test, and all other I/O pins of the IC chip are forced to a low voltage. In contrast, when a low voltage leakage test is conducted, a low voltage is applied to the pin under test, and all other pins are forced to a high voltage level. The pin under test, therefore, is always at a voltage different from that of the other pins. As a result, a time equal to the settling time of the pin under test must occur before either an accurate measurement of the leakage current at the pin may be made, or a determination may be made as to whether the pin is operating within acceptable tolerances. Settling time is a function of desired accuracy, and the R-C time constant is determined by the resistance of the test sensor resistor, and the sum of the capacitance of the test fixture and the I/O pin under test. Thus, for a given R-C time constant, when the test voltage is applied, voltage across the test sensor resistor follows a known exponential curve with respect to time. Further, the voltage is asymptotic to a final value, and takes time to reach the final value and settle before accurate measurements may be made.
Referring to the prior art circuit of FIG. 1, a precision D/A voltage source 10 is shown, the output of which is electrically connected to the input of a unity gain buffer amplifier 11. The output of the amplifier 11 in turn is electrically connected to one terminal of a precision high resistance current sensing resistor 12, and to the positive input of an instrumentation amplifier 13 which is used to monitor the performance of an I/O pin of an IC chip such as, by way of example, a CMOS dynamic random access memory (DRAM). The other terminal of the resistor 12 is electrically connected to the pole input of a single pole, single throw switch, and to the negative input of the amplifier 13. The output of the amplifier 13 is electrically connected to the input of an AID converter 15, the output of which is electrically connected to the input of a processor 16 that is used to calculate the leakage current of the memory module pin under test. The output of the switch 14 is electrically connected to one terminal of a test fixture capacitance 21, and to an I/O pin 22 of the unit under test (UUT). The other terminal of capacitance 21 is electrically connected to ground. The I/O pin 22 is represented by an I/O pin capacitance 23 and a source of leakage current 24 which are electrically connected in parallel to ground.
In operation, all I/O pins of a memory module except the pin under test are forced to either a high or a low voltage. The pin under test is forced to a voltage at the opposite end of the voltage range from that of the other pins. For CMOS DRAMs, by way of example, a high voltage for test purposes would be of the order of 5.0 volts, and a low voltage would be of the order of 0.0 volts. Assuming that all pins of a memory module except a pin under test are at 5.0 volts, the voltage source 10 would apply 0.0 volts through sense resistor 12 to switch 14. Upon the switch 14 being closed, a voltage would be applied to the pin under test. A delay time thereupon would have to occur to allow the test fixture capacitance 21 and the I/O pin capacitance 23 to discharge, and to allow the voltage across the current sensing resistor 12 to settle. Thereafter, A/D converter 15 would digitize the voltage received from instrumentation amplifier 13. The processor 16 would normalize the digitized value received from the A/D converter 15 as necessary, and divide the digitized value by the known resistance of the current sensing resistor 12 to provide an accurate measurement of the leakage current in the pin under test. The processor 16 then would indicate to the user whether the pin under test was within acceptable operating tolerances.
The settling time for the voltage applied across current sensing resistor 12 to a pin under test is the primary cause of excessive test times in measuring DC leakage currents. With CMOS devices, the leakage current is very small. That is, of the order of 100 nanoamps. Current sensing resistors having high resistance, therefore, are required to achieve measurable resolutions. With current sensing resistors having a resistance of the order of one megaohm and higher, the charge and discharge times of the I/O pins are high. The number of processor sample cycles which are required before an accurate measurement can be made, therefore, is high. Each of these factors contribute to the time required to conduct leakage current tests.
Prior art systems include that disclosed in U.S. Pat. No. 5,696,773 issued to Miller, which describes an apparatus used for performing leakage current tests on digital logic circuits. A parametric signal source employs two precision 1 M.OMEGA. current-sensing resistors per pin under test one for positive leakage currents and one for negative leakage currents. Each of the resistors is electrically connected in series with a D/A converter. The parametric signal source applies positive and negative parametric signals through Schottky diodes in series to a pin under test. Leakage currents are determined by dividing a voltage value at the positive and negative D/A converter outputs by the value of respective positive and negative current sensing resistors. The leakage currents then are compared with threshold leakage currents to determine acceptability. This system sources a voltage through a current-sensing resistor to the pin under test, and is subject to a pre-measurement settling time imposed by an R-C time constant.
U.S. Pat. No. 3,976,940 to Chau describes a testing circuit for providing digital stimuli to and receiving digital responses from I/O pins of a device under test at speeds up to 10 MHz. A pair of comparators for comparing the digital responses with minimum thresholds, and a multiplexer selecting between comparator outputs, allow continuous operation of the comparator and accommodates certain digital testing at high speeds up to 10 MHz. However, leakage testing is not conducted at such speeds. The circuit requires a plurality of FET transistors in parallel to achieve a low electronic switch "ON" resistance, and uses electromechanical relays which require at least 5 milliseconds to settle. Further, ECL technology is used which exhibits high power consumption at any given speed.
U.S. Pat. No. 3,702,967 to McPhail discloses a unipolar electronic test system for semiconductor devices that is operable in either current or voltage sourcing modes to sense leakage current flowing through a measurement resistor. This system sources a voltage through a current-sensing resistor to the pin under test, and is subject to a pre-measurement settling time imposed by an R-C time constant.
U.S. Pat. No. 4,004,222 to Gebhard discloses a test system for semiconductor SRAM cells. The detection of failed memory cells caused by inoperative memory cell pull-up elements, however, may be masked when normal stray capacitance on the nodes of the memory cell cannot be charged or discharged in an acceptable amount of time while a pattern test is being conducted. Methods are proposed to increase memory cell leakage during test by increasing photocurrent through illumination, and by elevating device temperature by as much as 80.degree. C. to quicken stray capacitance discharge time and shorten overall test time. However, the Gebhard system is not useable with commercial grade ICs, which are packaged and not rated for elevated temperatures.
U.S. Pat. No. 4,542,340 to Chakravarti discloses a method of measuring leakage currents in FET (field-effect transistor) semiconductor memory arrays using test sites formed in the kerf or cut regions of a wafer to test for acceptable leakage currents before sawing the wafer into chips to be packaged. The test points used in the Chakravarti method and system are not available after chips are cut from the wafer or packaged.
U.S. Pat. No. 4,595,875 to Chan et. al. discloses a leakage current and pin short detector for bipolar PROMs based on the inclusion of fault detection circuitry incorporated into the memory device. By applying a selected positive voltage to a test node, and measuring the resulting current into the node, deviations from a characteristic current-voltage (I-V) curve are observed to detect faulty devices. The Chan test circuit tests for leakage currents in memory cells, and not for I/O pin leakage currents as with the present invention.
U.S. Pat. No. 4,685,086 to Tran discloses an SRAM cell leakage detection circuit that is built into the memory chip itself. The tests which are conducted are based upon the principle of sensing complementary logic levels from properly operating SRAM cells (by way of example "01" or "10"), and by using a simple 2-input gate with appropriate thresholds to sense the absence of complimentary logic levels in defective cells. The Tran circuit is used only for memory cell testing, and not for I/O pin testing as with the present invention. Further, the Tran is not available for testing after a chip is packaged.
U.S. Pat. No. 4,800,332 to Hutchins discloses a reconfigurable IC with a capability to test for memory cell leakage. A test voltage is connected to a particular node of a memory device, while the rest of the memory device remains at a normal operating voltage. The test voltage is modulated to determine the voltage at which stored charge begins to leak between memory cells. Tests occur during memory device manufacture, and once the tests are concluded, the memory device is reconfigured for normal operation. Hutchins conducts only memory cell tests, and does not perform I/O pin tests as with the present invention. Further, the Hutchins test system is not available after a chip is packaged.
U.S. Pat. Nos. 4,841,482 and 4,860,261 to Kreifels et. al. disclose a circuit and method for leakage verification for flash EPROM/EEPROM memory cells. The circuit switches from a logic zero voltage to a non-zero test voltage on the word select lines of a memory cell, thereby enabling a measurement of leakage current on the bit lines of all cells coupled to the bit lines. The Kreifels' system and method test memory cells only, and not contact points outside a memory cell as does the present invention.
U.S. Pat. No. 5,132,929 to Ochii discloses an enhancement to an SRAM which allows leakage current measurements to occur in a test mode when the common V.sub.SS terminal of a memory cell flip-flop is brought to the V.sub.DD potential. A current sensing resistor is switched between the bit lines and the V.sub.DD potential, and a voltage reflecting leakage current is measured from one terminal of the current sensing resistor. Again, memory cell rather than I/O pin testing occurs, and the Ochii test terminals are not available after a chip is packaged.
U.S. Pat. No. 5,351,214 to Rouy discloses a circuit for the detection of bit line leakage by employing an output comparator having one input switchable between normal operation and a leakage reference in test mode, and a second input receiving the output of a memory array. When the leakage current threshold is selected during test mode, all word lines are simultaneously deselected, thus allowing only leakage currents on memory bit lines. The Rouy circuit only tests memory cells, and not I/O pins as does the present invention.
U.S. Pat. No. 5,491,665 to Sachdev discloses electronic circuitry fitted to an array of memory cells, whereby in a test mode all cells are accessed in parallel so that an I.sub.DDQ test may discover whether there is a defect in any of the cells. The Sachdev circuit tests memory cells only, and not I/O pins.
U.S. Pat. No. 5,659,511 to Huang discloses a method for measuring the leakage current of a DRAM capacitive junction by defining a large test memory cell comprised of numerous memory cells, and calculating the leakage current density of the large test memory cell by dividing the contact area of the bottom plate of the capacitor of the memory test cell, into the difference in junction leakage current between the memory cell transistor on and off states. The leakage current density of the memory test cell is taken as representative of the individual memory cells.
In contrast to the above prior art, the present invention conducts I/O pin leakage measurements after the IC chips are packaged, and assembled into IC modules. Further, the process of leakage current testing is accelerated by precharging the capacitance of the I/O pin under test to a voltage near its settled voltage, thereby reducing overall test time. More particularly, the present invention: 1) may switch either a ground potential or a selected voltage in electrical series with a low value resistor to the pin under test for rapid discharge and precharge of pin capacitance, thus shortening overall measurement time; 2) requires only one D/A converter as a voltage source for a single precision current-sensing resistor; and 3) identifies acceptable leakage current comparisons, and provides actual leakage current measurements which are suitable for manufacturing process monitoring. In addition, the present invention obviates the need for measurement corrections due to variations in temperature coefficients of diodes in series with the pin under test, and employs electronic switches having switch times less than one microsecond. Still further, the present invention is fully bipolar with respect to the polarity of voltage sourced and the direction of current measured through adaptation of operational amplifier technology. In addition, the present invention exhibits an economy of electronic components for increased reliability.